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TMU3100
USB Controller
GENERAL DESCRIPTION The TMU3100 is an 8-bit microprocessor embedded device tailored to the USB/PS2 Keyboard application. It includes an 8-bit RISC CPU core, 192-byte SRAM, Low Speed USB Interface and an 8K x 14 internal program OTP-ROM. FEATURE Compliance with the Universal Serial Bus specification v1.1 Built-in USB Transceiver and 3.3V regulator Support USB Suspend and Resume function One Control IN/OUT and two Interrupt IN endpoints PS2 compatible keyboard interface share with USB interface 192 byte internal SRAM 8K x 14 internal program OTP-ROM 8-bit RISC CPU core with only 36 instruction 3MHz instruction rate with 6MHz crystal oscillation 40/48 pin package
BLOCK DIAGRAM
USB Transceiver USB SIE USB Controller Keyboard Interface 8K x 14 Program OTP ROM
8-bit RISC CPU
192 Bytes SRAM
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tenx technology, inc.
Rev 1.4 2004/03/01
DS-TMU3100
PIN DESCRIPTION Name VDD VSS X1 X2 RESETn TESTn DP/PB[3] DM/PB[2] KSI[7:0] KSO[15:0] PA[3:0] PB[1:0] LED[3:0] VPP V33 I/O P P I O I I I/O I/O I O I/O I/O O I O Description 5V Power from USB cable Ground Crystal in (6MHz) Crystal out Chip reset (active low) Test Mode control (active low) USB positive data signal / General purpose I/O (pseudo open-drain) USB negative data signal / General purpose I/O (pseudo open-drain) Key scan input (with built-in pull-up resistor) Key scan output (open drain with pull up resistor) General purpose I/O (open drain with pull up resistor) General purpose I/O (pseudo open-drain) LED output (with serial 450 ohm resistor) OTP programming power 3.3V regulator output
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PIN ASSIGNMENT
VSS V33 DP/PB[3] DM/PB[2] PB[1] PB[0] PA[1] PA[0] VPP RESETn KSO[0] KSO[1] KSO[2] KSO[3] KSO[4] KSO[5] KSO[6] KSO[7] KSO[8] KSO[9]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TMU3100 PDIP 40 pin
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
X2 X1 VDD LED[0] LED[1] LED[2] KSI[0] KSI[1] KSI[2] KSI[3] KSI[4] KSI[5] KSI[6] KSI[7] KSO[15] KSO[14] KSO[13] KSO[12] KSO[11] KSO[10]
VSS V33 DP/PB[3] DM/PB[2] PB[1] PB[0] N.C. TESTn PA[1] PA[0] VPP RESETn KSO[0] KSO[1] KSO[2] KSO[3] KSO[4] KSO[5] N.C. PA[3] KSO[6] KSO[7] KSO[8] KSO[9]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TMU3100 SSOP 48 pin
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
X2 X1 VDD PA[2] LED[0] N.C. LED[1] LED[2] KSI[0] KSI[1] KSI[2] KSI[3] KSI[4] KSI[5] KSI[6] KSI[7] LED[3] N.C. KSO[15] KSO[14] KSO[13] KSO[12] KSO[11] KSO[10]
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FUNCTIONAL DESCRIPTION 1. CPU Core 1.1 Clock Scheme and Instruction Cycle The clock input (X1) is internally divided by two to generate Q1 state and Q2 state for each instruction cycle. The Programming Counter (PC) is updated at Q1 and the instruction is fetched from program ROM and latched into the instruction register in Q2. It is then decoded and executed during the following Q1-Q2 cycle. 1.2 Programming Counter (PC) and Stack The Programming Counter is 13-bit wide capable of addressing a 8K x 14 program ROM. As a program instruction is executed, the PC will contain the address of the next program instruction to be executed. The PC value is normally increased by one except the followings. The Reset Vector (0) and the Interrupt Vector (1) are provided for PC initialization. For CALL/GOTO instructions, PC loads its lower 12 bits from instruction word and the MSB from STATUS's bit 6. For RET/RETI/RETLW instructions, PC retrieves its content from the top level STACK. For the other instructions updating PC[7:0], the PC[12:8] keeps unchanged. The STACK is 13-bit wide and 6-level in depth. The CALL instruction and Hardware interrupt will push STACK level in order, While the RET/RETI/RETLW instruction pops the STACK level in order. 1.3 Addressing Mode There are two Data Memory Plane in CPU, R-Plane and F-Plane. The registers in R-Plane are write-only. The "MOVWR" instruction copy the W-register's content to those registers by direct addressing mode. Registers in F-Plane can be addressed directly or indirectly. Indirect Addressing is made by address "0", where FSR points to an actual address. The first half of F-Plane is also bit-addressable.
Program Memory 0000 0001 Reset Vector Interrupt Vector Program ROM Page 0 STATUS.6=0 0fff 1000 Program ROM Page 1 STATUS.6=1 3f 00
R-Plane 00
F-Plane Registers, STATUS.4=0/1 Bit addressable
MOVWR Instruction Write Only
1f 20 RAM, STATUS.4=0 RAM, STATUS.4=1 Bit addressable Bit addressable 3f 40
RAM, STATUS.4=0 RAM, STATUS.4=1 1fff 7f
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1.4 ALU and Working (W) Register The ALU is 8 bits wide and capable of addition, subtraction, shift and logical operations. In two-operand instructions, typically one operand is the W register, which is an 8-bit non-addressable register used for ALU operations. The other operand is either a file register or an immediate constant. In single operand instructions, the operand is either W register or a file register. Depending on the instruction executed, the ALU may affect the values of Carry(C), Digit Carry(DC), and Zero(Z) Flags in the STATUS register. The C and DC flags operate as a /Borrow and /Digit Borrow, respectively, in subtraction. 1.5 STATUS Register This register contains the arithmetic status of ALU and the page select for Program ROM and Data RAM. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. It is recommended, therefore, that only BCF, BSF and MOVWF instructions be used to alter the STATUS Register because these instructions do not affect those bits. 1.6 Interrupt Each interrupt source has its own enable control bit. An interrupt event will set its individual flag. If the corresponding interrupt enable bit has been set, it would trigger CPU to service the interrupt. CPU accepts interrupt in the end of current executed instruction cycle. In the mean while, A "CALL 0001" instruction is inserted to CPU, and the I-flag is set to prevent recursive interrupt nesting. The I-flag is cleared in the instruction after the "RETI" instruction. That is, at least one instruction in main program is executed before service the pending interrupt. The interrupt event is level trigged. F/W must clear the interrupt event register while serves the interrupt routine. 1.7 Instruction Set Each instruction is a 14-bit word divided into an OPCODE, which specified the instruction type, and one or more operands, which further specify the operation of the instruction. The instructions can be categorized as byte-oriented, bit-oriented and literal operations list in the following table. For byte-oriented instructions, "f" represents address designator and "d" represents destination designator. The address designator is used to specify which address in F-Plane is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If "d" is "0", the result is placed in the W register. If "d" is "1", the result is placed in the address specified in the instruction. For bit-oriented instructions, "b" represents a bit field designator, which selects the number of the bit affected by the operation, while "f" represents the address designator. For literal operations, "k" represents the literal or constant value. For "MOVWR" instruction, "r" specifies which address in R-Plane is to be used by the instruction. All instructions are single cycle except for program branches, which are two-cycle.
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Flag Cycles Affect Description 1 No operation 1 Go into standby mode, Clock oscillation stops 1 Clear and enable Watch Dog Timer 1 Move W to "r" 2 Return 2 Return from interrupt 1 Move W to "f" 1 Z Clear W 1 Z Clear "f" 1 C,DC,Z Subtract W from "f" 1 Z Decrement "f" 1 Z OR W with "f" 1 Z AND W with "f" 1 Z XOR W with "f" 1 C,DC,Z Add W and "f" 1 Move "f" to "w" 1 Z Test if "f" is zero 1 Z Complement "f" 1 Z Increment "f" 1 or 2 Decrement "f", skip if zero 1 C Rotate right "f" through carry 1 C Rotate left "f" through carry 1 Swap high/low nibble of "f" 1 or 2 Increment "f", skip if zero 1 Clear "b" bit of "f" 1 Set "b" bit of "f" 1 or 2 Test "b" bit of "f", skip if clear 1 or 2 Test "b" bit of "f", skip if set 2 Return, place Literal "k" in W 1 Move Literal "k" to W 1 Z OR Literal "k" with W 1 Z AND Literal "k" with W 1 C,DC,Z Add Literal "k" to W 1 Z XOR Literal "k" with W 2 Call subroutine "k" 2 Jump to branch "k"
Mnemonic NOP SLEEP CLRWDT MOVWR RET RETI MOVWF CLRW CLRF SUBWF DECF IORWF ANDWF XORWF ADDWF MOVFW TESTZ COMF INCF DECFSZ RRF RLF SWAPF INCFSZ BCF BSF BTFSC BTFSS RETLW MOVLW IORLW ANDLW ADDLW XORLW CALL GOTO
Op Code 00 0000 0 0000000 00 0000 0 0000011 00 0000 0 0000100 00 0000 0 0rrrrrr 00 0000 0 1000000 00 0000 0 1100000 00 0000 1 fffffff 00 0001 0 1000000 00 0001 1 fffffff 00 0010 d fffffff 00 0011 d fffffff 00 0100 d fffffff 00 0101 d fffffff 00 0110 d fffffff 00 0111 d fffffff 00 1000 0 fffffff 00 1000 1 fffffff 00 1001 d fffffff 00 1010 d fffffff 00 1011 d fffffff 00 1100 d fffffff 00 1101 d fffffff 00 1110 d fffffff 00 1111 d fffffff 010 00 bbb ffffff 010 01 bbb ffffff 010 10 bbb ffffff 010 11 bbb ffffff 011 000 kkkkkkkk 011 001 kkkkkkkk 011 010 kkkkkkkk 011 011 kkkkkkkk 011 100 kkkkkkkk 011 111 kkkkkkkk 10 kkkk kkkkkkkk 11 kkkk kkkkkkkk
r
f f f,d f,d f,d f,d f,d f,d f f f,d f,d f,d f,d f,d f,d f,d f,b f,b f,b f,b k k k k k k k k
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2. I/O Port 2.1 KSO[15:0] These pins are used as keyboard scan outputs. They have at least 4mA drive and sink strength.
Read Data
50uA
Pin 4mA
D Data
Q Data Register
CK /WR
KSO[15:0] 2.2 KSI[7:0] These pins are used as keyboard scan inputs. Each one of them has a pull up resistor. In addition, each KSI pin can cause Keyboard interrupt (KBDint) if the corresponding interrupt mask bit (KBDmask) is 0. The KBDint is asserted at the falling edge of KSI pin.
Read Data
Pin
KSI[7:0] 2.3 PA[3:0] These pins are similar to KSO pins, except data are read from pin. They can be used as input or open drain output.
50uA
Pin D Data Q Data Register 4mA Read Data
CK /WR
PA[3:0]
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2.4 PB[1:0] These pins are "Pseudo-Open-Drain" structure. In "Read-Modify-Write" instruction, CPU actually reads the output data register. In the others instructions, CPU reads the pin data. The so-called "Read-Modify-Write" instruction includes BSF, BCF and all instructions using F-Plane as destination. The PB[0] pin can also generate interrupt (PB0int) at its falling edge.
Read Register 1 OSC period delay D Data Q Data Register CK /WR
4mA
50uA
Pin
4mA
Read Pin
PB[1:0] 2.5 DP/PB[3] and DM/PB[2] These pins are similar to PB[1:0], except they share the pin with USB function. An extra control bit "PS2kbd" is used to enable the small pull-up current.
3.3V 3.3V Read Register 1 OSC period delay 4mA USB Output 4mA 50uA 20uA
D Data
Q Data Register
CK /WR PS2kbd
DP/PB[3] and DM/PB[2]
Read Pin
2.6 LED[3:0] These pins are used to drive LED. They are open-drain structure with a serial resistor. The typical resistor value is 420 ohm.
Pin
Read Data
D Data
Q Data Register
CK /WR
LED[3:0]
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3. Power Down Mode The power down mode is activated by SLEEP instruction. In power down mode, the crystal clock oscillation stops to minimize power consumption. Power down mode can be terminated by Reset or enabled Interrupts. 4. Watch Dog Timer The Watch Dog Timer (WDT) is disabled after Reset. F/W can use the CLRWDT instruction to clear and enable the Watch Dog Timer. Once enabled, the Watch Dog Timer overflow and generate a chip reset signal if no CLRWDT executed in a period of 4000000 oscillator's cycle (0.66 second for 6MHz crystal). The WDT does not work in Power Down Mode to provide wake-up function. It is only designed to prevent F/W goes into endless loop. 5. Timer 0 The Timer 0 is an 8-bit wide register of F-Plane. It can be read or written as any other register of F-Plane. Besides, Timer 0 increases itself periodically and reloads itself with a special value every time while roll over. The value to be load at roll over point is defined by "Timer 0 Reload" (T0RLD) register in the R-Plane. The period which Timer 0 increases itself is defined by "Timer 0 Pre-Scale" (T0PSCL) register in R-Plane, the default (0) mean 4 instruction cycles increase Timer 0. The Timer 0 also generates interrupt (T0int) while it rolls over. 6. USB Engine The USB engine includes the Serial Interface Engine (SIE), the low-speed USB I/O transceiver and the 3.3 Volt Regulator. The SIE block performs most of the USB interface function with only minimum support from F/W. Three endpoints are supported. Endpoint 0 is used to receive and transmit control (including SETUP) packets while Endpoint 1 and endpoint 2 are only used to transmit data packets. The USB SIE handles the following USB bus activity independently: 1. Bitstuffing/unstuffing 2. CRC generation/checking 3. ACK/NAK 4. TOKEN type identification 5. Address checking F/W handles the following tasks: 1. Coordinate enumeration by responding to SETUP packets 2. Fill and empty the FIFOs 3. Suspend/Resume coordination 4. Verify and select DATA toggle values 6.1 USB Device Address The USB device address register (USBadr) stores the device's address. This register is reset to all 0 after chip reset. F/W must write this register a valid value after the USB enumeration process. 6.2 Endpoint 0 receive After receiving a packet and placing the data into the Endpoint 0 receive FIFO (RC0FIFO), TMU3100 updates the Endpoint 0 status registers to record the receive status and then generates an Endpoint 0 receive interrupt (RC0int). F/W can read the status register for the recent transfer information, which includes the data byte count (RC0cnt), data direction (EP0dir), SETUP token flag (EP0set), packet toggle (RC0tgl) and data valid flag (RC0err). The received data is always stored into RC0FIFO and the RC0cnt is always updated for DATA packets following SETUP tokens. The data following an OUT token is written into the RC0FIFO, and the RC0cnt is updated unless Endpoint 0 STALL (EP0stall) is set or Endpoint 0 receive ready (RC0rdy) is cleared. The SIE clears the RC0rdy automatically and generates RC0int interrupt when the RC0cnt or RC0FIFO is updated. As long as the RC0rdy is cleared, SIE keep responding NAK to Host's Endpoint 0 OUT packet request. F/W should set the RC0rdy flag after the RC0int interrupt is asserted and RC0FIFO is read out. 6.3 Endpoint 0 transmit After detecting a valid Endpoint 0 IN token, TMU3100 automatically transmit the data pre-stored in the Endpoint 0 transmit FIFO (TX0FIFO) to the USB bus if the Endpoint 0 transmit ready flag (TX0rdy) is set and the EP0stall is cleared. The number of byte to be transmitted depends on the Endpoint 0 transmit byte count register (TX0cnt). The DATA0/1 token to be transmitted depends on the Endpoint 0 transmit toggle control 9
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bit (TX0tgl). After the TX0FIFO is updated, TX0rdy should be set to 1. This enables the TMU3100 to respond to an Endpoint 0 IN packet. TX0rdy is cleared and an Endpoint 0 transmit interrupt (TX0int) is generated once the USB host acknowledges the data transmission. The interrupt service routine can check TX0rdy to confirm that the data transfer was successful. 6.4 Endpoint 1/2 transmit Endpoint1 and Endpoint2 are capable of transmit only. These endpoints are enabled when the Endpoint1 / Endpoint2 configuration control bit (EP1cfg/EP2cfg) is set. After detecting a valid Endpoint 1/2 IN token, TMU3100 automatically transmit the data pre-stored in the Endpoint 1/2 transmit FIFO (TX1FIFO/TX2FIFO) to the USB bus if the Endpoint 1/2 transmit ready flag (TX1rdy/TX2rdy) is set and the EP1stall/EP2stall is cleared. The number of byte to be transmitted depends on the Endpoint 1/2 transmit byte count register (TX1cnt/TX2cnt). The DATA0/1 token to be transmitted depends on the Endpoint 1/2 transmit toggle control bit (TX1tgl/TX2tgl). After the TX1FIFO/TX2FIFO is updated, TX1rdy/TX2rdy should be set to 1. This enables the TMU3100 to respond to an Endpoint 1/2 IN packet. TX1rdy/TX2rdy is cleared and an Endpoint 1/2 transmit interrupt (TX1int/TX2int) is generated once the USB host acknowledges the data transmission. The interrupt service routine can check TX1rdy/TX2rdy to confirm that the data transfer was successful. 6.5 USB Control and Status Other USB control bits include the USB enable (ENUSB), Suspend (Susp), Resume output (RsmO), Control Read (CtrRD), and corresponding interrupt enable bits. The CtrRD should be set when program detects the current transfer is an Endpoint0 Control Read Transfer. Once this bit is set, the TMU3100 will stall an Endpoint0 OUT packet with DATA toggle 0 or byte count other than 0. Other USB status flag includes the USB reset interrupt (RSTint), Resume input interrupt (RSMint), and USB Suspend interrupt (SUSPint). 6.6 Suspend and Resume Once the Suspend condition is asserted, F/W can set the Susp bit to save the power consumption of USB Engine. F/W can further save the device power by force the CPU to go into the Power Down Mode. In the Power Down mode, the X'tal is stop, but CPU can be waken-up by the trigger of enabled interrupt's source, which includes RSMint, KBDint and PB0int. The TMU3100 send Resume signaling to USB bus when Susp=1 and RsmO=1. In the suspend mode, if a keyboard interrupt is asserted, F/W should send resume signal to wake up the USB bus.
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MEMORY MAP of F-Plane Name
Timer0 PCL ROMpage RAMbank Z DC C FSR PAD PBD PBD LED KSOL KSOH KSI GPR0 GPR1 ENUSB USBadr RC0int TX0int TX1int TX2int RSTint SUSPint RSMint KBDint PB0int T0int Susp RsmO EP1cfg EP2cfg CtrRD RC0rdy RC0tgl RC0err EP0dir EP0set RC0cnt TX0rdy TX0tgl EP0stall TX0cnt TX1rdy TX1tgl EP1stall TX1cnt TX2rdy TX2tgl EP2stall TX2cnt RC0FIFO SRAM
Address R/W Rst Description
01.7~0 02.7~0 03.6 03.4 03.2 03.1 03.0 04.6~0 05.3~0 06.3~0 06.3~0 07.3~0 08.7~0 09.7~0 0A.7~0 0E.7~0 0F.7~0 10.7 10.6~0 11.7 11.6 11.5 11.4 11.3 11.2 12.3 12.2 12.1 12.0 13.7 13.6 13.5 13.4 13.3 13.0 14.7 14.6 14.5 14.4 14.3~0 15.7 15.6 15.5 15.3~0 16.7 16.6 16.5 16.3~0 17.7 17.6 17.5 17.3~0 18~1F 20~7F R/W R/W R/W R/W R/W R/W R/W R/W R/W W R R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W 0 0 0 0 0 0 0 0 f f ff ff 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Timer 0 Program Counter [7~0] Program ROM Page Select (STATUS.6) SRAM Bank Select (STATUS.4) Zero Flag (STATUS.2) Decimal Carry Flag or Decimal /Borrow Flag (STATUS.1) Carry Flag or /Borrow Flag (STATUS.0) File Select Register to define Address in indirect addressing mode Port A output data Port B output data Port B output data or Port B pin data LED output Key Scan output [7~0] Key Scan output [15~8] Key Scan input [7~0] General Purpose Register 0 General Purpose Register 1 USB function enable (1) USB device address Endpoint 0 Receive Interrupt flag, write 0 to clear flag. Endpoint 0 Transmit Interrupt flag, write 0 to clear flag. Endpoint 1 Transmit Interrupt flag, write 0 to clear flag. Endpoint 2 Transmit Interrupt flag, write 0 to clear flag. USB Bus Reset Interrupt flag, write 0 to clear flag. USB Suspend Interrupt flag, write 0 to clear flag. USB Resume Interrupt flag, write 0 to clear flag. KeyBoard Interrupt flag, write 0 to clear flag. PB0 interrupt flag, write 0 to clear flag. Timer0 Interrupt flag, write 0 to clear flag. F/W force USB interface to go into suspend mode. F/W force USB interface send Resume signal in suspend mode. Set Endpoint 1 configuration. Set Endpoint 2 configuration. H/W will stall an invalid OUT token during Control Read transfer. Endpoint 0 ready for receive, clear by H/W while RC0int occurs. 1: received DATA1 packet; 0: received DATA0 Packet. Endpoint 0 received data error. 1: IN transfer; 0: OUT/SETUP transfer. SETUP Token indicator. Received data byte count. Endpoint 0 ready for transmit, clear by H/W while TX0int occurs. Endpoint 0 transmit DATA1/DATA0 packet. Endpoint 0 will stall OUT/IN packet while this bit is 1. Endpoint 0 transmit byte count. Endpoint 1 ready for transmit, clear by H/W while TX1int occurs. Endpoint 1 transmit DATA1/DATA0 packet. Endpoint 1 will stall IN packet while this bit is 1. Endpoint 1 transmit byte count. Endpoint 2 ready for transmit, clear by H/W while TX2int occurs. Endpoint 2 transmit DATA1/DATA0 packet. Endpoint 2 will stall IN packet while this bit is 1. Endpoint 2 transmit byte count. Endpoint 0 Receive Buffer (8 Bytes) Internal RAM (96 Bytes x 2 Banks)
0 0 0 0 0 0 0 0 0 0 0 0 -
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MEMORY MAP of R-Plane Name
T0RLD T0PSCL PWRdwn WDTe KBDmask TESTreg TX0FIFO TX1FIFO TX2FIFO RC0ie TX0ie TX1ie TX2ie RSTie SUSPie PS2kbd RSMie KBDie PB0ie T0ie
Address R/W Rst Description
01.7~0 02.3~0 03 04 05.7~0 0F.3~0 18~1F 20~27 28~2F 11.7 11.6 11.5 11.4 11.3 11.2 12.4 12.3 12.2 12.1 12.0 W W W W W W W W W W W W W W W W W W W W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Timer0 overflow reload value Timer0 Pre-Scale, 0:divided by 2, 1:divided by 4, ... 7:divided by 256, 8:divided by 1 (Time base is 2*instruction cycle) Write this register to enter Power-Down Mode Write this register to clear WDT and enable WDT Mask KSI[7:0] interrupt function while the corresponding bit is "1" Test Mode control, keep 0 in normal mode Endpoint 0 Transmit Buffer (8 Bytes) Endpoint 1 Transmit Buffer (8 Bytes) Endpoint 2 Transmit Buffer (8 Bytes) RC0 Interrupt enable TX0 Interrupt enable TX1 Interrupt enable TX2 Interrupt enable USB Reset Interrupt enable Suspend Interrupt enable Select PS2 keyboard Mode RSM Interrupt enable Keyboard Interrupt enable PB[0] Interrupt enable Timer 0 Interrupt enable
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APPLICATION CIRCUIT 40PIN Package The circuitry is only for Keyboard reference.
R2 1.5K
1 2
VDD
U1
VSS V33 X1 DP/PB[3] DM/PB[2] PB[1] PB[0] PA[1] PA[0] VPP KSI[2] RESETn KSI[3] KSO[0] KSO[1] KSO[2] KSO[3] KSO[4] KSO[5] KSO[6] KSO[7] KSO[8] KSO[9] KSI[4] KSI[5] KSI[6] KSI[7] KSO[15] KSO[14] KSO[13] KSO[12] KSO[11] KSO[10] KSI[0] KSI[1] 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD LED[0] LED[1] LED[2] 38 37 36 35 39 X2 40
C2 20P X1 6MHz C3 20P CAP NUM SCROLL D1 D2 D3
C1
0.1uF 1uF~10uF
3 4 5 6 7 8 9
DP/CLK DM/DATA
C2 C1 R1 100K C3 C4 C5 C6 C7 C14 C13 C12 C11 C15
C4 R0 R1 R2 R3 R4 R5 R6 R7 C17 C16 C0 C9 C8 C10 4.7uF
C5 0.1uF
10 11 12 13 14 15 16 17 18 19 20
TMU3100
Programming PIN: VPP,VDD,X1,RESTn,TESTn,PB[0],KSI[3],KSI[6],KSI[7],VSS
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ABSOLOUTE MAXIMUM RATINGS GND= 0V Name Symbol Maximum Supply Voltage VDD Maximum Input Voltage Vin Maximum output Voltage Vout Maximum Operating Temperature Topg Maximum Storage Temperature Tstg RECOMMEND OPERATING CONDITION at Ta=-20 to 70,GND= 0V Name Symb. Min. Supply Voltage VDD 4.5 Input "H" Voltage Vih 3.5 Input "L" Voltage Vil1 0
Range -0.3 to 5.5 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -5 to +70 -25 to +125
Unit V V V
Max. 5.5 5.5 0.8
Unit V V V
DC CHARACTERISTICS at Ta=-25 ,VDD=5.0V, VSS= 0V, Fosc=6MHz Name Symb. Min. Operating current Icc Suspend current Isus Output High Voltage Voh1 Voh2 Output Low Voltage Vol RESET pull up resistor Rrst KSI pull up resistor Rksi LED sink current Iled V33 output voltage V33
Typ. 5.5 360 4.0 4.5 0.4 31 46 5.5 3.28
Max.
Unit mA uA V V V Kohm Kohm mA V
Condition Fosc=6MHz No load Ioh=30uA Ioh=4mA Iol=15mA (Vrst=3.38v) Vled=3.2V
AC CHARACTERISTICS at Ta=-25 ,VDD=5.0V, VSS= 0V, Fosc=6MHz Name Symb. Min. Max. Unit DP/DM rising time Trise 75 300 ns DP/DM falling time Tfall 75 300 ns DP,DM cross point Vx 1.3 2.0 V Note: All USB transceiver characteristics can meet USB1.1 spec.
Note
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Package Diagrams 40 PIN P_ DIP
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48 PIN SSOP
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PAD locations
PB0 PB1
DM
DP
V33
VSS
X2
X1 VDD
PA2
LED0
1
TSTN PA1 PA0 VPP RSTN
LED1 LED2 KSI0
KSI1 KSI2
Die size:2170*2130 um
KSO0 KSO1 KSO2 KSO3 KSO4 KSO5
KSI3 KSI4 KSI5
KSI6 KSI7 LED3
PA3 KSO6 KSO7
KSO8 KSO9 KSO10 KSO11 KSO12
KSO13KSO14 KSO15
(2170,2130)um
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Rev 1.4 2004/03/01
DS-TMU3100
Probe Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Pad Name VSS V33 DP DM PB1 PB0 TSTN PA1 PA0 VPP RSTN KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 PA3 KSO6 KSO7 KSO8 KSO9 X Y Probe Coordinate Coordinate Number 1150.50 2021.00 23 902.50 2021.00 24 782.50 2021.00 25 588.50 2021.00 26 467.50 2021.00 27 334.50 2021.00 28 109.00 1795.50 29 109.00 1678.50 30 109.00 1506.50 31 109.00 1386.50 32 109.00 1246.50 33 109.00 1006.5 34 109.00 874.50 35 109.00 754.50 36 109.00 622.50 37 109.00 492.50 38 109.00 334.50 39 334.50 109.00 40 467.50 109.00 41 588.50 109.00 42 836.50 109.00 43 957.50 109.00 44 Pad Name KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 LED3 KSI7 KSI6 KSI5 KSI4 KSI3 KSI2 KSI1 KSI0 LED2 LED1 LED0 PA2 VDD X1 X2 X Y Coordinate Coordinate 1087.50 109.00 1205.50 109.00 1335.50 109.00 1575.50 109.00 1708.50 109.00 1829.50 109.00 2061.00 336.50 2061.00 467.50 2061.00 587.50 2061.00 826.50 2061.00 946.50 2061.00 1066.50 2061.00 1186.50 2061.00 1306.50 2061.00 1542.50 2061.00 1662.50 2061.00 1793.50 1835.50 2021.00 1714.50 2021.00 1514.50 2021.00 1393.50 2021.00 1271.50 2021.00
Ordering Information
Ordering Code TMU3100CC TMU3100DC TMU3100SSC Package Type Chip 40 Pin DIP Package 48 Pin SSOP Package Operating Range Commercial Commercial Commercial
18
tenx technology, inc.
Rev 1.4 2004/03/01

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